1. Field of the Invention
The present invention relates generally to lithographic methods and systems. More specifically it relates to methods to reduce overlay uncertainty by improving the imaging of patterned resist features.
2. Background of the Invention
The manufacture of products containing microscopic devices, such as memory chips, microprocessors, optical devices, micro-electromechanical devices (MEMS), and numerous other types of devices (hereinafter referred to as “chips”), typically requires lithographic patterning in which the microscopic features are in part defined by a photoresist (“resist”) layer applied during chip processing. The resist layer is usually patterned by exposure to a radiation source, which selectively exposes microscopic areas of the resist by use of a patterned mask (in the case of optical or x-ray lithography) or a programmed exposure (“direct write”) (in the case of electron beam lithography).
Once the resist is patterned, the resist pattern is transferred to permanent layers in the chip, creating features with similar size and shape to the resist features. In this manner, permanent features of the chip such as metal wires, insulating regions, or silicon structures are fabricated. Subsequent to permanent feature patterning, the remaining resist is typically removed. In many devices, up to about 20 different resist patterns (hereinafter termed “mask levels”) may be employed to fully define all the patterns (hereinafter termed “mask levels”) may be employed to fully define all the features of the device. Each mask level may pattern a different feature of a device or circuit. FIG. 1 shows a method for forming device features in two mask levels, well known to practicioners in the art. In FIG. 1(a), patterning with a first mask level results in the definition of resist feature 2, residing on top of silicon layer 4, which, in turn, is on top of oxide layer 6. In FIG. 1(b), the shape of resist feature 2 is transferred to the silicon layer, resulting in formation of element 8, e.g., a transistor gate. The transfer of the resist shape into the silicon layer may be accomplished by many techniques well known to skilled practicioners. FIG. 1(c) illustrates a top-down view after a second mask level is applied, resulting in the definition of resist mask 10, containing aperture 12, and residing on top of patterned transistor gate 8 and oxide 4 (not shown). In FIG. 1(d), metal wire 14 is formed in the region of aperture 12, with subsequent removal of mask 10. In this example, the shape of resist feature 12 is transferred to the metal wire 14 which contacts transistor gate 8.
In the above example, because, the placement of the transistor gate 8 is defined by a different mask level than that of the metal wire 14, it is critical that the mask level used for placing the metal wire is aligned with respect to the transistor level. For instance, width W of transistor element 8 may be less than 1 um, requiring that the placement of the metal line be somewhat more precisely defined in order to ensure that it overlaps the transistor to the appropriate extent. To accomplish this, the resist features in the second mask level must be aligned to the existing transistor structure already formed.
A ubiquitous problem in the prior art is the lack of precision in aligning the pattern of a given mask level to the underlying device features already present (referred to as overlay uncertainty). In prior art, many mask levels have features referred to as alignment marks (hereafter also referred to as “marks”), which can be used by a human or by an instrument to adjust the pattern placement of a given level. Typically, an alignment mark feature is not part of the actual working device, but is nevertheless transferred from resist into materials permanently incorporated in the device. Thus, resist feature 20 depicted in FIG. 2(a) is transferred into the silicon layer, creating alignment mark 22, as illustrated in FIG. 2(b). During a subsequent mask level patterning shown in FIG. 2(c), a resist alignment mark 24 is created, whose relative distance L from the silicon alignment mark 22 can be measured. Alignment marks may be significantly larger than many device elements and therefore are easier than the latter to image, providing a more convenient method of aligning device features formed in different mask levels, as opposed to measuring the distance between device elements directly. For instance, mark 24 typically might be several thousand nanometers (nm) in size, while resist feature 2 (FIG. 1) might be 100 nm in width, rendering it invisible to the unaided eye.
FIG. 3(a) illustrates this point further, where silicon transistor element 32 and silicon alignment mark 30 are fabricated with a desired spacing between them, using a first mask. After resist is applied for the next mask level, resist alignment mark 40 is formed by any of several well known lithographic processes. In addition, resist element 42 is formed to define the placement of an additional device feature, e.g., an oxide isolation mesa 44, near transistor element 32. FIG. 3(b) illustrates the device structure after mesa 44 formation, showing permanent oxide mark 40′. Referring again to FIG. 3(a), those skilled in the art understand that the spacing between transistor 32 and mark 30 is known, inasmuch as this is determined by the design of the mask used for their fabrication. Similarly, the relative positions of resist mark 40 and element 42 are determined by the mask design used to from the latter elements. Thus, measurement of the distance L2 between silicon mark 30 and resist mark 40, provides a simple method to determine the separation of resist element 42 and transistor 32, which may be too small to measure directly. Were a serious misalignment to be detected, the patterned resist could be removed without harming structures 30 and 32. This would forestall incorrect placement of mesa 44 with respect to transistor 32, and afford the possibility of subsequently re-applying the resist element in order to achieve a better alignment of mesa 44 and transistor 32.
As is well known in the art, typical resists used to pattern chips are comprised at least in part of an organic polymer, which is transparent to the light used in equipment employed to measure alignment. When resist alignment marks are placed on reflective surfaces, e.g., metals, semiconductors, or certain insulators, light may be reflected back through the resist marks, reducing the ability to image the marks, especially at the mark edge. This renders it difficult to measure the relative alignment of different mask levels. Furthermore, as device feature sizes continue to shrink for many products such as memory and microprocessor chips, the tolerance for misalignment becomes much stricter. Referring again to FIG. 3(b), if it were critical that mesa 44 be within 2000 nanometers (nm) of transistor 32, an alignment error of 300 nm may be tolerable. However, if the separation required were only 250 nm, the 300 nm tolerance would clearly be unacceptable. In the latter case, a shift of 300 nm could easily result in formation of mesa 44 too far from transistor 32. Furthermore, using current resist processes, it may be difficult to image marks with sufficient resolution to ensure that a 250 nm difference in mark position can be accurately measured. Thus, in light of the foregoing it will be appreciated that there is a need to be able to more accurately measure the placement of alignment marks on devices during their processing.